1. Field of the Invention
This invention generally relates to signal level detection circuitry and, more particularly, to a system and method for an improved electrical signal level detection circuit and associated detection method.
2. Description of the Related Art
An electrical signal level detection function is commonly achieved using an analog peak detector, forward biasing of a diode, bipolar base-emitter (BE) junction, or FET-charged capacitor until the DC voltage of the capacitor approaches the peak level of the AC signal. A large time constant is achieved by maximizing the size of the capacitor and minimizing the discharge current. Various factors that tend to degrade the accuracy of these measurements include device mismatches, changes in temperature, varying bandwidths, and signal content. One approach to addressing these inaccuracies involves the use of conventional closed loop methods. However, use of feedback is problematic for high speed signals, effectively forcing response times to be too slow. Various feedforward techniques allow faster response time, but these techniques require large internal devices, consuming die area or use of external components, and the measurements are not sufficiently repeatable.
FIG. 1 is a schematic drawing of a simple peak detector circuit (prior art). The diode 100 acts as a rectifier, and in combination with an operational amplifier 102, more closely mimics the response on an ideal diode. The purpose of the circuit is to detect the maximum positive peak voltage at Vin 108. The measurement is provided as a DC voltage at Vout 110. When the input is positive, it is amplified by the operational amplifier, biasing the diode. Current is applied to the load (RL 104 and CL 106) and, the feedback makes the output voltage Vout 110 equal to the input 108.
When the input voltage is negative, there is a negative voltage on the diode, effecting an open circuit. There is no current into the load and the opamp output voltage is zero. Practically, when the input becomes negative, the output of the operational amplifier can easily approach the negative supply voltage (not shown), causing saturation. Since it takes a finite time to recover from saturation, the frequency response of the circuit is impaired.
The use of non-linear circuit devices (i.e., a diode) makes signal level measurements very susceptible to variations in temperature and device process variations. Even with tightly controlled operating conditions and inclusion of temperature compensation techniques, the absolute accuracy of a conventional level detector varies. Further, the architecture is not easily portable from one device to another.
The high speed of signals, combined with the need to charge a large capacitor, causes conventional detector circuits to consume a large amount of power. The large time constant associated the detector hold time is achieved by using large capacitor values. However, as circuit dimensions get smaller, the relative size of these large-value storage capacitors is becoming larger.
New applications and markets are emerging that require better accuracy of level detection, lower power per port, a higher port density—achieved through more ports per device, smaller device size, and a smaller net footprint on the printed circuit board (PCB), by minimizing the number of external components such as filter capacitors.
It would be advantageous if a level detection method existed that addressed the above-mentioned speed and accuracy requirements, while not increasing die area and power.
It would be advantageous if level detection circuit existed to provide a lower power, more accurate, more portable, and more flexible signal level detector than is possible with conventional methods.